In an interface circuit transmitting or receiving data between, for example, circuit boards or between large scale integrated circuits (LSI), a multi-phase clock has been used to sample the data to a plurality of timing.
For example, in a high speed signal transmission system, the receiving device samples data transmitted from the transmitting device by using a multi-phase clock so as to receive the data. In the system using the multi-phase clock, a phase interpolation circuit may be used to control the phase of the sampling clock.
The phase interpolation circuit determines the phase of an output signal (e.g., sampling clock) by interpolating the phase of a plurality of input signals (e.g., reference clock) based on a phase code.
Related technologies are disclosed in, for example, Japanese Laid-Open Patent Publication No. 2006-140639 and Japanese National Publication of International Patent Application No. 2009-529271.